DocumentCode
2871008
Title
Invited: Circuit scaling limits for ultra-large-scale integration
Author
Meindl, J. ; Ratnakumar, K. ; Gerzberg, L. ; Saraswat, Krishna
Author_Institution
Stanford University, Stanford, CA, USA
Volume
XXIV
fYear
1981
fDate
18-20 Feb. 1981
Firstpage
36
Lastpage
37
Abstract
This report will define a hierarchy of limits governing ULSI and describe circuit performance to project minimum dimensions for NMOS transistors, polysilicon resistors and interconnections. Possible future levels of ULSI will also be assessed.
Keywords
Electron devices; Integrated circuit technology; MOS devices; MOSFETs; Microelectronics; Silicon; Solid state circuits; Ultra large scale integration; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1981.1156150
Filename
1156150
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