Boost the Performance of RMT

Simultaneous multithreading processor permits multiple issues from different threads at the same time, which provides nature support for fault-tolerance by executing threads redundantly. SRT is such architecture which detects faults by comparing the store instruction results between master threads and the copied slave threads. Later in SRTR, function of recovery is added. In SRT and SRTR instruction queue (IQ) is a critical resource and slave threads can use IQ more efficiently, since master threads may encounter D-cache miss, while slave threads may not. Slave threads can get load instructions results from master threads and never commit store instructions results to storage. In master threads, instructions dependent on D-cachemiss-load instructions may stay in IQ for hundreds of cycles without any performance contributions. This paper proposed DDDI (delay dispatching dependent instructions) which means that instructions of master threads that dependent on unresolved D-cache-miss-load instructions can´t be dispatched into IQ until the load instruction is completed. Experiments show that the method is effective for improving the IQ utilization and processor performance.