A Self-Calibrated On-chip Phase-Noise-Measurement Circuit with -75dBc Single-Tone Sensitivity at 100kHz Offset

Author

Khalil, Waleed ; Bakkaloglu, Bertan ; Kiaei, Sayfe

Author_Institution

Intel, Chandler, AZ

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

546

Lastpage

621

Abstract

An on-chip phase-noise-measurement circuit with single-tone measurement sensitivity of -75dBc at 100kHz offset from carrier is presented. The circuit uses a delay-line and mixer frequency discriminator and can operate up to 2GHz input frequency. This module does not rely on a reference clock and, with on-line self calibration, its accuracy is stabilized across gate-delay variations.

Keywords

discriminators; integrated circuit measurement; integrated circuit noise; mixers (circuits); noise measurement; phase noise; 100 kHz; 2 GHz; delay-line; gate-delay variations; mixer frequency discriminator; on-chip phase-noise-measurement circuit; online self calibration; reference clock; single-tone measurement sensitivity; Circuit noise; Clocks; Delay lines; Frequency; Inverters; Jitter; Noise measurement; Output feedback; Phase measurement; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373536

Filename

4242507

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2871135