DocumentCode
2871143
Title
A bipolar 2500-gate subnanosecond masterslice LSI
Author
Horiba, Y. ; Nakaya, M. ; Kato, Shigeo ; Tsukamoto, Kazuya ; Sakurai, Haruaki ; Kondo, Toshiaki
Author_Institution
Mitsubishi Electric Corporaton, Itami, Japan
Volume
XXIV
fYear
1981
fDate
18-20 Feb. 1981
Firstpage
228
Lastpage
229
Abstract
A masterslice LSI, developed for random logic, providing an average delay time of 0.8ns/gate, with power dissipation of 0.5mW/gate, will be covered in this paper.
Keywords
Delay effects; Impurities; Ion implantation; Large scale integration; Logic circuits; Logic gates; Packaging; Power dissipation; Voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1981.1156159
Filename
1156159
Link To Document