DocumentCode :
2871435
Title :
A 34 µm2 DRAM cell fabricated with a 1 µm single-level polycide FET technology
Author :
Hu Chao ; Dennard, R. ; Mon Tsai ; Wordeman, M. ; Cramer, A.
Author_Institution :
IBM Research Center, Yorktown Heights, NY, USA
Volume :
XXIV
fYear :
1981
fDate :
18-20 Feb. 1981
Firstpage :
152
Lastpage :
153
Abstract :
Exploratory one-device dynamic RAM arrays, fabricated with N-channel single-level polycide (WSI2) technology with minimum feature size of 1μm, will be discussed.
Keywords :
Circuit noise; Clamps; Delay effects; Electrical resistance measurement; FETs; Noise figure; Noise measurement; Noise reduction; PSNR; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1981.1156177
Filename :
1156177
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2871435
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