• DocumentCode
    2871811
  • Title

    A 32b VLSI CPU chip

  • Author

    Beyers, J. ; Dohse, L. ; Fucetola, J. ; Kochis, R. ; Lob, C. ; Taylor, Gareth ; Zeller, E.

  • Author_Institution
    Hewlett-Packard Company, Fort Collins, CO, USA
  • Volume
    XXIV
  • fYear
    1981
  • fDate
    18-20 Feb. 1981
  • Firstpage
    104
  • Lastpage
    105
  • Abstract
    This paper will cover a fully-integrated 32b VLSI processing system with six VLSI chips, containing up to 600,000 transistors/chip. Chips are: 32b CPU, I/O processor, memory controller, 128Kb RAM and 528Kb ROM.
  • Keywords
    Clocks; Decoding; Hardware; Logic arrays; Pipeline processing; Programmable logic arrays; Read only memory; Registers; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1981.1156198
  • Filename
    1156198
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2871811