An FET chip-level cell combiner

Further improvements in power GaAs FETs at Ku-band and higher frequencies must be accompanied by improved circuit techniques. Conventional cell combining and matching techniques are simply inadequate when applied to the problem of multiple cell combining at Ku-band frequencies. Due to the low impedance level, cell phasing and interaction problems, the number of cells which can be combined successfully decreases rapidly with increasing frequency. An approach is required that applies circuit-level power combining concepts (integral isolation) to the problem of cell combining to yield high combining efficiency. This paper will describe a chip-level cell combining technique, with integral isolation characteristics, which attempts to solve these problems.