Title :
Design methodologies for VLSI
Author_Institution :
University of California, Berkeley, CA, USA
Abstract :
As the complexity of ICs increases at an exponential rate, the cost and time of design has similarly escalated. Among the evolving layout methods to be compared are the use of standard cells, gate arrays, high level symbolic and structured design techniques.
Keywords :
Circuit testing; Costs; Design automation; Design methodology; Logic arrays; Logic design; Logic testing; Microelectronics; Technology management; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1981.1156220
