DocumentCode :
2872388
Title :
Double-edge Triggered Level Converter Flip-Flop with Feedback
Author :
Seyedi, Azam-Sadat ; Afzali-Kusha, Ali
Author_Institution :
Nanoelectron. Center of Excellence, Tehran Univ., Tehran
fYear :
2006
fDate :
16-19 Dec. 2006
Firstpage :
44
Lastpage :
47
Abstract :
In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DELCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.
Keywords :
circuit feedback; flip-flops; pulse generators; double-edge pulse generator; double-edge triggered level converter flip-flop; feedback; pass gate transistors; power consumption; stack transistors; Circuits; Clocks; Delay; Energy consumption; Feedback; Flip-flops; Inverters; Low voltage; MOSFETs; Pulse generation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2006. ICM '06. International Conference on
Conference_Location :
Dhahran
Print_ISBN :
1-4244-0764-8
Electronic_ISBN :
1-4244-0765-6
Type :
conf
DOI :
10.1109/ICM.2006.373263
Filename :
4243644
Link To Document :
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