• DocumentCode
    2872419
  • Title

    Self-aligned transistor with sidewall base electrode

  • Author

    Nakamura, T. ; Miyazaki, Toshimasa ; Takahashi, Satoshi ; Kure, T. ; Okabe, Toshiya ; Nagata, M.

  • Author_Institution
    Hitachi Central Research Laboratory, Tokyo, Japan
  • Volume
    XXIV
  • fYear
    1981
  • fDate
    18-20 Feb. 1981
  • Firstpage
    214
  • Lastpage
    215
  • Abstract
    This report will cover a multiple-self-aligned bipolar structure with negligible parasitic junction capacitances, suitable for scaled-down I2L-VLSI. A fabricated model indicared that CCBwas reduced by 75% and βuand βdwas increased 4 times compared to a conventional structure.
  • Keywords
    Boron; Electrodes; Epitaxial layers; Etching; Fabrication; Frequency; Laboratories; Parasitic capacitance; Silicon; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1981.1156232
  • Filename
    1156232
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2872419