Title :
Reconfigurable Low Power FIR Filter based on Partitioned Multipliers
Author :
Shah, Farhat Abbas ; Jamal, Habibullah ; Khan, Muhammad Akhtar
Author_Institution :
Nat. Eng. & Sci. Comm., Islamabad
Abstract :
This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.
Keywords :
FIR filters; field programmable gate arrays; multiplying circuits; programmable filters; system-on-chip; VLSI digital signal processing systems; Xilinx Vertex-II FPGA 2s200fg256-6; finite-impulse response filter; low power programmable FIR filter; partitioned data dependent multiplier; partitioned multipliers; switching activity reduction; system-on-a-reprogrammable-chip; Clocks; Computer architecture; Digital signal processing; Field programmable gate arrays; Filtering; Finite impulse response filter; Power engineering and energy; Power engineering computing; Sprites (computer); System-on-a-chip; Partitioned data dependent multiplier (PDDM); System on chip (SoC); System-on-a-reprogrammable-chip (SoRC); partitioned multiplier (PM);
Conference_Titel :
Microelectronics, 2006. ICM '06. International Conference on
Conference_Location :
Dhahran
Print_ISBN :
1-4244-0764-8
Electronic_ISBN :
1-4244-0765-6
DOI :
10.1109/ICM.2006.373273
