A Very Fast and Low Power Pseudo-Incrementer for Address Bus Encoder/Decoder

This paper presents a very fast yet low power pseudo incrementer structure which may be used in address bus encoders/decoders. This structure, which is based on the ripple carry incrementer, is much faster than the incrementer. Using this structure, the delay and the power of address bus encoders/decoders may be reduced considerably. Analytical and synthesis results show that the structure is faster than current incrementer circuits while its circuit area and power are much smaller than those of current fast incrementers.