Title :
HMOS-CMOS technology
Author :
Yu, Kaiyuan ; Chwang, R. ; Bohr, M. ; Seidenfeld, M. ; Berglund, C.
Author_Institution :
Intel Corp., Aloha, OR, USA
Abstract :
This paper will report on a bulk CMOS technology based on HMOS, affording such features as high resistivity P substrate diffused wells and 2μm channel length N and P channel devices. A 4K static RAM test vehicle using this approach has demonstrated 25ns access time and microwatt standby power.
Keywords :
CMOS process; CMOS technology; Circuits; Delay; Design optimization; Doping; EPROM; MOS devices; Optimized production technology; Parasitic capacitance;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1981.1156239
