• DocumentCode
    2872553
  • Title

    A delay model and speculative architecture for pipelined routers

  • Author

    Peh, Li-Shiuan ; Dally, William J.

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    255
  • Lastpage
    266
  • Abstract
    This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific flow control method employed the delay of the flow control credit path, and the sharing of crossbar ports across virtual channels. Motivated by this model, we introduce a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router. Simulations using our pipelined model give results that differ considerably from the commonly assumed `unit-latency´ model which is unreasonably optimistic. Using realistic pipeline models, we compare wormhole and virtual-channel flow control. Our results show that a speculative virtual-channel router has the same per-hop router latency as a wormhole router while improving throughput by up to 40%
  • Keywords
    multiprocessor interconnection networks; pipeline processing; interconnection networks; microarchitecture; performance; pipeline models; pipelined routers; router delay model; speculative virtual-channel router; Bandwidth; Computer architecture; Delay effects; Delay estimation; Laboratories; Multiprocessor interconnection networks; Pipelines; Switches; Throughput; Virtual colonoscopy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on
  • Conference_Location
    Monterrey
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1019-1
  • Type

    conf

  • DOI
    10.1109/HPCA.2001.903268
  • Filename
    903268