Title :
Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics
Author :
Rahmani, E. ; Pajouhi, Z. ; Kazemian-Amiri, N. ; Afzali-Kusha, A.
Author_Institution :
Nanoelectron. Center of Excellence, Univ. of Tehran, Tehran
Abstract :
In this paper, a new domino logic structure whose architecture is based on a leakage biased (LB) domino circuit is introduced. The proposed technique improves the performance and the dynamic power consumption of the circuits. In addition, the number of transistors is reduced leading to a lower silicon area. Simulations are done for various circuits. Compared to the LB method, in a full adder circuit, the delay is reduced more than 25%; also, the dynamic and the static powers have reduced slightly.
Keywords :
adders; integrated logic circuits; low-power electronics; domino logic structure; dynamic power consumption; full adder circuit; leakage-biased domino circuit; low-delay characteristics; low-power characteristics; CMOS logic circuits; Capacitance; Dynamic voltage scaling; Energy consumption; Inverters; Leakage current; Logic circuits; Power dissipation; Silicon; Threshold voltage;
Conference_Titel :
Microelectronics, 2006. ICM '06. International Conference on
Conference_Location :
Dhahran
Print_ISBN :
1-4244-0764-8
Electronic_ISBN :
1-4244-0765-6
DOI :
10.1109/ICM.2006.373282
