A high-speed divide-by-32/33 frequency divider in 0.25μm CMOS technology

Author

Yang, Wen-Rong ; Cao, Jia-Lin ; Ran, Feng ; Qing, Ting-Gao

Author_Institution

Microelectron. R&D Center, Shanghai Univ., China

fYear

2004

fDate

18-21 Aug. 2004

Firstpage

554

Lastpage

557

Abstract

A high-speed divide-by-32/33 frequency divider has been developed in a 0.25μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed divider can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25μm CMOS model, simulation results indicate that the maximum input frequency of the divider is up to 3.2GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6mA at input frequency of 2.5GHz.

Keywords

CMOS logic circuits; UHF integrated circuits; circuit noise; frequency dividers; high-speed integrated circuits; logic design; low-power electronics; switching circuits; 0.25 micron; 2.5 GHz; 2.5 V; 3.2 GHz; 4.6 mA; CMOS technology; high frequency operation; high-speed divide-by-32-33 frequency divider; low-power consumption; maximum input frequency; source-coupled logic; switching noise reduction; CMOS logic circuits; CMOS technology; Circuit noise; Counting circuits; Energy consumption; Flip-flops; Frequency conversion; Frequency synthesizers; Gallium arsenide; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology, 2004. ICMMT 4th International Conference on, Proceedings

Print_ISBN

0-7803-8401-6

Type

conf

DOI

10.1109/ICMMT.2004.1411589

Filename

1411589