• DocumentCode
    2872869
  • Title

    A NoC Traffic Suite Based on Real Applications

  • Author

    Liu, Weichen ; Xu, Jiang ; Wu, Xiaowen ; Ye, Yaoyao ; Wang, Xuan ; Zhang, Wei ; Nikdast, Mahdi ; Wang, Zhehui

  • Author_Institution
    Hong Kong Univ. of Sci. & Technol., Hong Kong, China
  • fYear
    2011
  • fDate
    4-6 July 2011
  • Firstpage
    66
  • Lastpage
    71
  • Abstract
    As benchmark programs for microprocessor architectures, network-on-chip (NoC) traffic patterns are essential tools for NoC performance assessments and architecture explorations. The fidelity of NoC traffic patterns has profound influence on NoC studies. For the first time, this paper presents a realistic traffic benchmark suite, called MCSL, and the methodology used to generate it. The publicly released MCSL benchmark suite includes a set of realistic traffic patterns for 8 real applications and covers popular NoC architectures. It captures not only the communication behaviors in NoCs but also the temporal dependencies among them. MCSL benchmark suite can be easily incorporated into existing NoC simulators and significantly improve NoC simulation accuracy. We developed a systematic traffic generation methodology to create MCSL based on real applications. The methodology uses formal computational models to capture both communication and computation requirements of applications. It optimizes application mapping and scheduling to faithfully maximize overall system performance and utilization before extracting realistic traffic patterns through cycle-accurate simulations. Experiment results show that MCSL benchmark suite can be used to study NoC characteristics more accurately than traditional random traffic patterns.
  • Keywords
    electronic engineering computing; microprocessor chips; network-on-chip; MCSL traffic benchmark suite; NoC performance assessments; NoC traffic patterns; cycle-accurate simulations; formal computational models; microprocessor architectures; network-on-chip; systematic traffic generation; Benchmark testing; Computational modeling; Computer architecture; Delay; Performance evaluation; Scheduling; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Chennai
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4577-0803-9
  • Electronic_ISBN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2011.49
  • Filename
    5992461