• DocumentCode
    2872928
  • Title

    A Fixed Delay Infinite-Bit Split Adder Architecture and Its Application in Real-Time Image Processing

  • Author

    Hajjar, Amjad Fuad

  • Author_Institution
    Dept. of Electr. & Comput. Eng., King Abdulaziz Univ., Jeddah
  • fYear
    2006
  • fDate
    16-19 Dec. 2006
  • Firstpage
    194
  • Lastpage
    197
  • Abstract
    A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.
  • Keywords
    adders; image processing; computer arithmetic; fixed delay split adder; gate delays; infinite-bit split adder architecture; real-time image processing; Added delay; Application software; Computational complexity; Computer architecture; Concurrent computing; Digital arithmetic; Hardware; Image processing; Parallel architectures; Silicon; approximate addition; binary adders; computer arithmetic; high-speed adders; image processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2006. ICM '06. International Conference on
  • Conference_Location
    Dhahran
  • Print_ISBN
    1-4244-0764-8
  • Electronic_ISBN
    1-4244-0765-6
  • Type

    conf

  • DOI
    10.1109/ICM.2006.373300
  • Filename
    4243682
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2872928