DocumentCode :
2872962
Title :
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz
Author :
Biswas, Arnab K. ; Bulusu, A. ; Dasgupta, S.
Author_Institution :
Dept. of Electron. & Comput. Eng., Indian Inst. of Technol., Roorkee, India
fYear :
2011
fDate :
4-6 July 2011
Firstpage :
108
Lastpage :
113
Abstract :
This paper proposes and describes a new output buffer which uses a comparator to switch one of the parallel output stages. This scheme can be used to control the output resistance of the buffer, which is useful for output signal monitoring. This paper shows that we can actually minimize the switching noise or ringing noise by the same method. We have also compared the results with a conventional buffer and showed that the new buffer is relatively superior. For realistic simulation we have changed the effective inductance and load capacitance of both buffer and showed that our buffer works better than the conventional one in those conditions also. We have done Monte Carlo analysis of both buffer and observed that the new buffer works better in different process variation conditions as well. Simulations have been carried out in 90 nm technology node using HSPICE.
Keywords :
Monte Carlo methods; buffer circuits; circuit noise; comparators (circuits); switching circuits; HSPICE; Monte Carlo analysis; comparator; frequency 83.3 MHz; minimum signal switching noise; output buffer; resistance cotnrol; ringing noise; signal monitoring; size 90 nm; Equivalent circuits; Inductance; MOS devices; Noise; Oscillators; Resistance; Switches; low ringing; minimum switching noise; output buffer; reduced SSN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
ISSN :
2159-3469
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
Type :
conf
DOI :
10.1109/ISVLSI.2011.15
Filename :
5992468
Link To Document :
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