Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC

This paper presents a low-power, high speed complementary input folded regulated cascode operational transconductance amplifier (OTA) designed for the 10 bit, 150MSPS parallel pipeline ADC. The OTA plays an important role in the ADC, because of its conversion rate and power consumption are limited by the performance of the OTA. The designed ADC in this paper employs parallel pipeline architecture based on double sampling sampled hold (DSSH) technique, and shares the OTA between two channels of the ADC. The folded cascode OTA consists of fully differential and regulated cascode gain boosting technique. Besides, a Common Mode Feed Back (CMFB) circuit was introduced and some methods are concerned to improve the performance. Then, by proper optimization of the layout design, OTA´s mismatch was reduced up-to a great extent. With 1.8 V power supply, using the CMOS9T5V 180nm process technology, the simulation shows that the open-loop gain of the OTA is 90.39 dB, the phase margin (PM) is 63.85° with the unity gain bandwidth (UGB) of 700.7 MHz. The power consumption of this OTA is only 3.24 mW, which significantly reduces the whole power consumption of the parallel pipeline ADC.