Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage

In this paper, we explore the use of coplanar waveguide interconnects in FPGAs to improve wire delay and reduce the number of used routing tracks. We propose a new FPGA architecture in which RF receivers and transmitters are employed. In addition, we present an algorithm to re-route some suitable wires with RF interconnects. Experimental results show that using this technique, required routing tracks are reduced by 7% on average, and the delay of wire segments that use RF resources is decreased by 69.4%. These benefits are earned in cost of area and power consumption overhead that are negligible for large FPGAs.