Title :
AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS
Author :
Morooka, Yoshikazu ; Mori, Shigeru ; Miyamoto, Hiroshi ; Yamada, Michihiro
Keywords :
Circuit faults; Circuit testing; DRAM chips; Decoding; Error correction; Laboratories; Large scale integration; Memory architecture; Random access memory; Registers;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519718
