A Quantitative Study on Layer-2 Packet Processing on a General Purpose Processor

Author

Salehi, Mostafa E. ; Rafati, Ramin ; Baharvand, Farshad ; Fakhraie, Sied Mehdi

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran

fYear

2006

fDate

16-19 Dec. 2006

Firstpage

218

Lastpage

221

Abstract

In this paper, we present a quantitative study that investigates implementation of a layer-2 switching application on a general purpose processor (GPP). The objective is to better understand the main challenges and tradeoffs in using such processors for packet processing applications. The goal of this study is to identify the architectural guidelines for successful development of an application specific instruction processor (ASIP) for such applications. To asses the performance of switching of packets with various lengths, a LEON2 RISC processor has been chosen as a GPP. The obtained results are compared together based on detailed instruction level profiling of the mentioned application.

Keywords

application specific integrated circuits; general purpose computers; microprocessor chips; reduced instruction set computing; LEON2 RISC processor; application specific instruction processor; general purpose processor; instruction level profiling; layer-2 packet processing; layer-2 switching; Application software; Application specific processors; Engines; Guidelines; Helium; Optical computing; Optical packet switching; Packet switching; Reduced instruction set computing; Switches; Layer-2 switching; network processors; packet processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2006. ICM '06. International Conference on

Conference_Location

Dhahran

Print_ISBN

1-4244-0764-8

Electronic_ISBN

1-4244-0765-6

Type

conf

DOI

10.1109/ICM.2006.373306

Filename

4243688