Title :
A 6K-gate CMOS gate array
Author :
Kobayashi, Takehiko ; Tago, H. ; Moriya, Takehiro ; Yamamoto, Seiichi
Author_Institution :
Toshiba Corporation, Kawasaki, Japan
Abstract :
An array, with Propagation delays well into the subnanosecond region, featuring 2μm design rules and double layer metalization, will be reported.
Keywords :
CMOS technology; Clocks; Contact resistance; Etching; Integrated circuit interconnections; Inverters; Planarization; Plasma measurements; Semiconductor device measurement; Silicon;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156280
