Title :
A 6,000-gate CMOS gate array
Author :
Itoh, Takayuki ; Takechi, Masaru ; Fujita, Masayuki ; Ikuzaki ; Masaki, A. ; Asano, Masahiro ; Murata, Shotaro ; Horiguchi, Shogo ; Yoshimura, Hiroyuki
Author_Institution :
Hitachi Device Development Center, Tokyo, Japan
Abstract :
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
Keywords :
Circuit noise; Delay effects; Inverters; Laboratories; Logic arrays; Logic circuits; Noise figure; Power supplies; Silicon; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156281
