A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

A current-mode clock distribution network (CMCDN) for low-power low-skew on-chip clock distribution is presented in this paper. A novel low-power current-mode receiver circuit with common-mode correction for the CM-CDN is also presented. The CM-CDN and associated receiver circuit are designed and optimized in 90 nm CMOS process with 1V supply voltage. The performance of the proposed CM-CDN is analyzed and simulated under parameter variations using corner analysis as well as Monte Carlo model files provided by the foundry. It is shown that the worst case skew of a 1-Level H-Tree CM-CDN is 21 ps considering on-chip process variation whereas skew of an optimized voltage-mode CDN (VM-CDN) in the same process is 33 ps. Power consumption of the proposed CM-CDN operating at 4GHz is 6.28 mW which is 57% less as compared to the voltage-mode CDN. Also for the same input impedance of 200Ω, the proposed receiver consumes a power of 521.4 μW which is 35% less than that of state of the art current-mode receiver.