• DocumentCode
    2873616
  • Title

    HMOS III technology

  • Author

    Liu, Siyuan ; Chao-Hsiang Fu ; Atwood, Greg ; Langston, Jerrod ; Hazani, E. ; Haiping Dun ; Beinglass, I. ; Sachdev, S. ; Fuchs, Kerstin

  • Author_Institution
    Intel Corporation, Santa Clara, CA, USA
  • Volume
    XXV
  • fYear
    1982
  • fDate
    10-12 Feb. 1982
  • Firstpage
    234
  • Lastpage
    235
  • Abstract
    Scaled HMOS III technology, featuring 1 μm electrical channel lengths fabricated with direct-step lithography, will be discussed. Procedure affords low-resistance gate electrodes and refractory metal contacts to allow shrinking of existing designs without increasing parasitic resistances.
  • Keywords
    Automatic control; Energy consumption; Geometry; Logic design; MOS devices; Microprocessors; Pins; Random access memory; Read-write memory; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1982.1156308
  • Filename
    1156308
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2873616