Title :
A Global Optimization for Scan Chain Insertion at the RT-level
Author :
Zaourar, Lilia ; Kieffer, Yann ; Aktouf, Chouki
Author_Institution :
Lab. LIP6/Soc, Univ. Pierre et Marie Curie, Paris, France
Abstract :
We present a new method for scan chain ordering specifically tailored for RTL-scan and its unique challenges.
Keywords :
logic circuits; logic design; RTL-scan; global optimization; scan chain insertion; Computational modeling; Electronic mail; Logic gates; Optimization; Proposals; Routing; Testing; Design For Test; high-level testing; optimization;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.46
