• DocumentCode
    2873626
  • Title

    A Global Optimization for Scan Chain Insertion at the RT-level

  • Author

    Zaourar, Lilia ; Kieffer, Yann ; Aktouf, Chouki

  • Author_Institution
    Lab. LIP6/Soc, Univ. Pierre et Marie Curie, Paris, France
  • fYear
    2011
  • fDate
    4-6 July 2011
  • Firstpage
    321
  • Lastpage
    322
  • Abstract
    We present a new method for scan chain ordering specifically tailored for RTL-scan and its unique challenges.
  • Keywords
    logic circuits; logic design; RTL-scan; global optimization; scan chain insertion; Computational modeling; Electronic mail; Logic gates; Optimization; Proposals; Routing; Testing; Design For Test; high-level testing; optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Chennai
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4577-0803-9
  • Electronic_ISBN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2011.46
  • Filename
    5992507
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2873626