• DocumentCode
    2873631
  • Title

    High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam

  • Author

    Lomte, Rashmi K. ; Bhaskar, P.C.

  • Author_Institution
    Electron. Technol. Dept., Shivaji Univ., Kolhapur, India
  • fYear
    2011
  • fDate
    4-6 July 2011
  • Firstpage
    323
  • Lastpage
    324
  • Abstract
    Convolution and Deconvolution has many applications in digital signal processing. Multipliers and dividers are basic blocks in convolution and deconvolution implementation. They consumes much of time. With advances in technology, many researchers have tried and are trying to design multipliers and dividers which offer either of the following-high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier and divider. In this paper, direct method is used to find convolution and deconvolution. Discrete linear convolution of two finite length sequences using Urdhva Triyagbhyam algorithm is presented here. Same algorithm is also used for deconvolution to improve speed. This design approach efficiently and accurately speeds up computation without compromising with area.
  • Keywords
    convolution; deconvolution; digital signal processing chips; dividing circuits; multiplying circuits; Urdhva Triyagbhyam algorithm; deconvolution implementation; digital signal processing; discrete linear convolution; divider; finite length sequence; multiplier; power consumption; Algorithm design and analysis; Convolution; Deconvolution; Delay; Digital signal processing; Signal processing algorithms; Convolution; Deconvolution; Non restoring algorithm; Urdhva Triyagbhyam;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Chennai
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4577-0803-9
  • Electronic_ISBN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2011.10
  • Filename
    5992508