Author :
Konishi, Satoshi ; Matsunaga, J. ; Ohtani, T. ; Sekine, Masakazu ; Isobe, M. ; Iizuka, Tetsuya ; Uchida, Yasuo ; Kohyama, S.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.
Keywords :
CMOS process; Decoding; Delay lines; Driver circuits; Fabrication; Latches; MOS devices; Random access memory; Read-write memory; Semiconductor device measurement;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156311
