DocumentCode
2873681
Title
A 64Kb CMOS RAM
Author
Konishi, Satoshi ; Matsunaga, J. ; Ohtani, T. ; Sekine, Masakazu ; Isobe, M. ; Iizuka, Tetsuya ; Uchida, Yasuo ; Kohyama, S.
Author_Institution
Toshiba Corp., Kawasaki, Japan
Volume
XXV
fYear
1982
fDate
10-12 Feb. 1982
Firstpage
258
Lastpage
259
Abstract
This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.
Keywords
CMOS process; Decoding; Delay lines; Driver circuits; Fabrication; Latches; MOS devices; Random access memory; Read-write memory; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1982.1156311
Filename
1156311
Link To Document