A reconfigurable computing architecture for microsensors

Microsensor systems are described that support reconnaissance, surveillance and target acquisition (RSTA) operations. Since communication bandwidth on a microsensor is limited by the power constraints imposed by desired sensor lifespan, the amount of data that can be transmitted is minimal. Therefore, much of the signal processing needed to implement the desired functionality must be performed within the aggressive size, power and weight constraints of the microsensor itself. Furthermore, it is desired that these microsensors be inexpensive and have a very small logistics tail. In order to make the solution inexpensive, it is asserted that a common and open architecture for microsensors should be developed so that a wide range of sensor heads can be seamlessly interchanged utilizing a common piece of hardware. This not only allows the development cost to be shared among the widest possible range of applications but results in a generic sensor processor that can be configured at time of deployment. This paper describes a computing architecture developed by Sanders which employs FPGA technology married with a general purpose processor. In addition, this effort has demonstrated the applicability of FPGA technology to a widespread DoD application space and shown it to be a technology discriminator for future microsensor systems. The motivation for this common architecture for microsensors (CAμS) the CAμS architecture, the baseline acoustic algorithm implemented, and the results of the fielded system, which achieved more than four orders of magnitude reduction in size*weight*power over the ARL DUNES testbed, are discussed. Future work is also described