Title :
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis
Author :
Soumya, J. ; Venkatesh, Putta ; Chattopadhyay, Santanu
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Abstract :
This paper presents a heuristic technique based on Particle Swarm Optimization (PSO) for finding the router positions from the available positions within the chip floor plan, so that the communication cost between cores is minimized, satisfying link length and router port constraints. Comparison with regular mesh-based NoC architectures and with custom architectures having routers positioned at the corners of the cores have been carried out. The results show significant reduction in communication cost.
Keywords :
network-on-chip; particle swarm optimisation; PSO; application-specific network-on-chip synthesis; flexible router placement; heuristic technique; mesh-based NoC architectures; particle swarm optimization; Approximation algorithms; Computer architecture; Conferences; Genetic algorithms; Particle swarm optimization; Topology; Very large scale integration; Application Specific Network on Chip; Communication cost; Particle Swarm Optimization;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.26