A bit-serial implementation of the international data encryption algorithm IDEA

Author

Leong, M.P. ; Cheung, O.Y.H. ; Tsoi, K.H. ; Leong, P.H.W.

Author_Institution

Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China

fYear

2000

fDate

2000

Firstpage

122

Lastpage

131

Abstract

A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 2¹⁶+1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks

Keywords

cryptography; pipeline processing; reconfigurable architectures; Intel Pentium II; XCV1000-6 device; Xilinx Virtex XCV300-6; bit-serial architecture; bit-serial implementation; high-speed networks; international data encryption algorithm IDEA; multiplication modulo; online encryption; software implementation; system clock rate; Asynchronous transfer mode; Clocks; Computer architecture; Computer science; Cryptography; Hardware; High-speed networks; Software performance; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-7695-0871-5

Type

conf

DOI

10.1109/FPGA.2000.903399

Filename

903399