Death of the RLOC?

Author

Singh, Satnam

Author_Institution

Xilinx Inc., San Jose, CA, USA

fYear

2000

fDate

2000

Firstpage

145

Lastpage

152

Abstract

“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realised on FPGAs using Xilinx´s place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound effect on custom computing machines which can be more easily targeted from high level specification languages like Handle-C and JHDL without requiring clumsy layout information to be accommodated at the language level

Keywords

circuit layout CAD; field programmable gate arrays; macros; simulated annealing; FPGAs; Handle-C; JHDL; Xilinx´s place and route software; custom computing machines; level specification languages; relational placement macro; simulated annealing; Circuit simulation; Computational modeling; Computer architecture; Fabrics; Field programmable gate arrays; Hardware design languages; Java; Signal processing algorithms; Simulated annealing; Specification languages;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-7695-0871-5

Type

conf

DOI

10.1109/FPGA.2000.903401

Filename

903401