Title :
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis
Author :
Sinha, Sharad ; Dhawan, Udit ; Lam, Siew Kei ; Srikanthan, Thambipillai
Author_Institution :
Nanyang Technol. Univ., Singapore, Singapore
Abstract :
Hardware binding plays an important role in the performance of a design on FPGAs. Good timing performance requires that the hardware binding be as efficient as possible. It is often acceptable to let the area increase within a tolerance limit if the timing could be improved. In this paper, we propose a new hardware binding algorithm.. It performs simultaneous FU and register binding incorporating device-specific delay information for functional units and multiplexers. The proposed approach, implemented within a C to RTL framework has resulted in significant improvement in maximum achievable clock frequency compared to previously proposed Weighted Bipartite Matching and Compatibility Path Based algorithms. The associated increase in area is also within a very tight margin and hence quite acceptable even when there is an area constraint. Also, when compared to WBM and CPB methods, the proposed algorithm improves clock period on average by 17.6% and 9.7% respectively without any penalty in area. When compared with ECPB algorithm, clock period is improved by 5.6% on average at a small area cost of 5.5%.
Keywords :
field programmable gate arrays; CPB methods; FPGA; RTL framework; WBM methods; clock frequency; compatibility path based algorithms; critical path delay reduction; device-specific delay information; hardware binding algorithm; weighted bipartite matching algorithm; Algorithm design and analysis; Clocks; Delay; Hardware; Registers; Table lookup; Delay reduction; FPGA; High Level Synthesis;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.18