DocumentCode :
2873875
Title :
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths
Author :
Ram, D. S Harish ; Bhuvaneswari, M.C. ; Logesh, S.M.
Author_Institution :
Dept. of Electron. & Commun. Eng., Amrita Vishwa Vidyapeetham Univ., Coimbatore, India
fYear :
2011
fDate :
4-6 July 2011
Firstpage :
290
Lastpage :
295
Abstract :
The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search.
Keywords :
genetic algorithms; high level synthesis; DFG; IIR benchmark; NSGA II; delay optimization; evolutionary technique; high level synthesis; multiobjective power; nondominated sorting genetic algorithm II; standard benchmark data-flow graphs; Benchmark testing; Biological cells; Delay; Genetic algorithms; Optimization; Schedules; Behavioral synthesis; System level design; evolutionary computation; high-level synthesis; low power design; multi-objective optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
ISSN :
2159-3469
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
Type :
conf
DOI :
10.1109/ISVLSI.2011.55
Filename :
5992521
Link To Document :
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