Title :
A 64b floating point processor
Author_Institution :
Hewlett-Packard Co., Cupertino, CA, USA
Abstract :
A floating point chip set capable of one-million scalar operations per second will be reported. The set consists of add/subtract, multiply and divide chips.
Keywords :
CMOS logic circuits; CMOS process; Clocks; Data buses; Logic design; Microcomputers; Pins; Process design; Propagation delay; Registers;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156327
