Title :
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
Author :
Chen, Chia-I ; Huang, Juinn-Dar
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this work, we thoroughly investigate all existing woks about distributed register-file micro architecture family with variant inter-island delay models, and the experimental results indicate that our work does provide better synthesis outcome than the prior art.
Keywords :
integrated circuit interconnections; memory architecture; architectural synthesis frameworks; distributed register-file microarchitecture family; variant inter-island delay models; Art; Computer architecture; Delay; Integrated circuit interconnections; Microarchitecture; Minimization; System performance;
Conference_Titel :
VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on
Conference_Location :
Chennai
Print_ISBN :
978-1-4577-0803-9
Electronic_ISBN :
2159-3469
DOI :
10.1109/ISVLSI.2011.19
