Title :
Improving the FPGA design process through determining and applying logical-to-physical design mappings
Author :
Graham, Paul ; Hutchings, Brad ; Nelson, Brent
Author_Institution :
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
Abstract :
While creating CCM-platform-independent, device-specific readback support for hardware debugging in the JHDL design environment, we have found that knowing how design elements from the user´s logical design were mapped to their counterparts in the FPGA physical implementation can be very useful and important. With only a partial mapping from the logical to the physical, we would not be able to provide users of JHDL with a complete view of what their circuit is doing during hardware execution via FPGA readback mechanisms. As an example of how to determine logical-to-physical mappings of FPGA circuits, we outline the process of supporting readback for Xilinx XC4000 and Virtex designs under the JHDL environment. This same process should apply to other structural design methodologies and for other purposes. Synthesis methodologies require some additional steps to relate how the high-level HDL design mapped to the FPGA vendors´ library elements
Keywords :
computer debugging; field programmable gate arrays; hardware description languages; logic design; CCM-platform-independent device-specific readback support; FPGA design process; FPGA vendor library elements; JHDL design environment; Virtex designs; Xilinx XC4000; hardware debugging; high-level HDL design; logical design; logical-to-physical design mappings; structural design methodologies; synthesis methodologies; Circuits; Debugging; Design optimization; Energy consumption; Field programmable gate arrays; Hardware; Organizing; Pins; Process design; Table lookup;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
DOI :
10.1109/FPGA.2000.903429