Improving the FPGA design process through determining and applying logical-to-physical design mappings

While creating CCM-platform-independent, device-specific readback support for hardware debugging in the JHDL design environment, we have found that knowing how design elements from the user´s logical design were mapped to their counterparts in the FPGA physical implementation can be very useful and important. With only a partial mapping from the logical to the physical, we would not be able to provide users of JHDL with a complete view of what their circuit is doing during hardware execution via FPGA readback mechanisms. As an example of how to determine logical-to-physical mappings of FPGA circuits, we outline the process of supporting readback for Xilinx XC4000 and Virtex designs under the JHDL environment. This same process should apply to other structural design methodologies and for other purposes. Synthesis methodologies require some additional steps to relate how the high-level HDL design mapped to the FPGA vendors´ library elements