Title :
32K and 16K MOS RAMs using laser redundancy techniques
Author :
Smith, Ross ; Bateman, B. ; Sharp, P. ; Dishaw, J. ; Smudski, J.
Author_Institution :
Intel Corporation, Santa Clara, CA, USA
Abstract :
NMOS static RAMs (4906 × 8b and 2048 × 8b) incorporating laser redundancy techniques will be described. The approach involves the use of conservative 4μm design rules and conventional projection printer lithography with large die sizes and multiple redundant elements.
Keywords :
Circuit faults; DRAM chips; Decoding; Fault tolerance; Fuses; Latches; Paper technology; Read-write memory; Redundancy; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156342
