DocumentCode :
2874349
Title :
Pattern recognition and reconstruction on a FPGA coprocessor board
Author :
Männer, R. ; Sessler, M. ; Simmler, H.
Author_Institution :
Mannheim Univ., Germany
fYear :
2000
fDate :
2000
Firstpage :
325
Lastpage :
326
Abstract :
High energy accelerator labs use huge detector systems to track particles. The ATLAS detector at CERN, Geneva (Switzerland), will provide complex three-dimensional images. A trigger system at the detector output is used to reduce the amount of data to a manageable size. Each trigger applies certain filter algorithms to select the very rare physically interesting events. The algorithm presented, processes data from a special detector called TRT, to generate a trigger decision within ≈10 ms. System supervisors then decide together with other results whether the event will be rejected or passed to the next trigger level. Due to the restricted execution time for calculating the decision, fast pattern recognition algorithms are required. These algorithms require a high I/O bandwidth and high computing power. These reasons and the high degree of parallelism make it best suited for custom computing machines
Keywords :
field programmable gate arrays; high energy physics instrumentation computing; image processing equipment; object detection; pattern recognition; ATLAS detector; FPGA coprocessor board; TRT; complex three-dimensional images; computing power; custom computing machines; detector output; fast pattern recognition algorithms; filter algorithms; high I/O bandwidth; high energy accelerator labs; huge detector systems; parallelism; particle tracking; pattern recognition; restricted execution time; special detector; system supervisors; three-dimensional images; trigger decision; trigger level; trigger system; Bandwidth; Coprocessors; Detectors; Field programmable gate arrays; Filters; Image reconstruction; Parallel processing; Particle accelerators; Particle tracking; Pattern recognition;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
Type :
conf
DOI :
10.1109/FPGA.2000.903438
Filename :
903438
Link To Document :
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