DocumentCode
2874468
Title
Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond
Author
Yamashita, T. ; Shiga, K. ; Hayashi, T. ; Umeda, H. ; Oda, H. ; Eimori, T. ; Inuishi, M. ; Ohji, Y. ; Eriguchi, K. ; Nakanishi, K. ; Nakaoka, H. ; Yamada, T. ; Nakamura, M. ; Miyanaga, I. ; Kajiya, A. ; Kubota, M. ; Ogura, M.
Author_Institution
Renesas Technol. Corp., Hyogo, Japan
fYear
2004
fDate
26-28 July 2004
Firstpage
123
Lastpage
124
Abstract
For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.
Keywords
CMOS integrated circuits; MOSFET; leakage currents; nanotechnology; reliability; 65 nm; boron penetration; electrical stress; fabrication process; gate oxide integrity; gate-oxide reliability; leakage current; low operational power devices; low standby power devices; miniaturization effect; optimized transistor characteristics; scaled CMOSFET; short-channel pMOSFET; Boron; CMOSFETs; Degradation; Etching; Leakage current; MOSFETs; Plasma applications; Plasma devices; Plasma properties; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Future of Electron Devices, 2004. International Meeting for
Print_ISBN
0-7803-8423-7
Electronic_ISBN
0-7803-8424-5
Type
conf
DOI
10.1109/IMFEDK.2004.1566439
Filename
1566439
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