DocumentCode
2874671
Title
A subnanosecond cycle time chip in Josephson technology
Author
Mukherjee, Arjun
Author_Institution
IBM Research Center, Yorktown Heights, NY, USA
Volume
XXV
fYear
1982
fDate
10-12 Feb. 1982
Firstpage
240
Lastpage
241
Abstract
THIS PAPER will describe the design and performance of a subnanosecond cycle time logic chip in Josephson technology. A data processing circuit, implemented in 2.5pm Josephson Current Injection Logic (CIL)?? has been tested at cycle times as small as 665ps The chip power dissipation was about 350pW. The circuit contained OR gates, AND gates, EX-OR gates and latches - equivalent to 102 logic gates, consisting of 177 devices. The gates were powered by an ac power supply2 which was regulated on chip3. The latch circuits were of a self-resetting type, designed for this application.
Keywords
Circuit testing; Data processing; Josephson effect; Josephson junctions; Latches; Logic circuits; Logic devices; Logic testing; Power supplies; Superconducting logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1982.1156366
Filename
1156366
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