A 256K dynamic MOS RAM with alpha immune and redundancy

A 256K DYNAMIC MOS RAM, with a metal folded bit line structure, employing full Vcc store circuits for alpha immunity and with redundancy bits fory ield enhancement, will be described. The device has been assembled in a standard 300mil wide 16pin DIP. The RAM has 256 refresh cycles at 4ms intervals. As shown in Figure 1, the memory cell array is divided into four blocks with horizontal metal bit lines split by 512 sense amplifiers on either side of the array and short polycide word lines running vertically. The metal folded bit line structure was found to be superior to the diffused open bit line for alpha immunity, by a soft error analysis??. The folded bit line structure also has less coupling noise213 and a larger effective area for a memory cell capacitance.