Sparse distributed memory implementations on tree shape parallel neurocomputer

Author

Hämäläinen, Timo

Author_Institution

Electron. Lab., Tampere Univ. of Technol., Finland

fYear

1996

fDate

4-6 Sep 1996

Firstpage

539

Lastpage

548

Abstract

This paper presents two different realizations of a sparse distributed memory (SDM) model. For parallelization purposes, addressing, storage and retrieval operations are explained in detail and some existing implementations in various computing platforms are considered before introducing the tree shaped parallel computer, TUTNC (Tampere University of Technology Neural Computer). The architecture and main features of TUTNC are presented in order to map SDM to the system in columnwise and rowwise manner. Mappings are compared in terms of measured execution time with different parameter sets. Speedup and performance estimations are also given for a larger system. The results show, that SDM can be well parallelized in TUTNC

Keywords

distributed memory systems; memory architecture; neural nets; parallel machines; TUTNC; Tampere University of Technology Neural Computer; addressing; execution time; parallelization; performance estimations; retrieval; sparse distributed memory; speedup; storage; tree shape parallel neurocomputer; Biological system modeling; Computational modeling; Concurrent computing; Counting circuits; Hamming distance; Humans; Random access memory; Read-write memory; Shape; Sparse matrices;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks for Signal Processing [1996] VI. Proceedings of the 1996 IEEE Signal Processing Society Workshop

Conference_Location

Kyoto

ISSN

1089-3555

Print_ISBN

0-7803-3550-3

Type

conf

DOI

10.1109/NNSP.1996.550061

Filename

550061