Design and performance of a VLSI implemented 16 channel FDM demultiplexer for onboard processing

A digital demultiplexer structure based on a half-band prototype filter design is introduced for communication satellites. A unidirectional filter cell serves as a key processing element for a tree structured hierarchical multistage approach. Its time-multiplexed realization is presented with focus on minimization of the gate count for a VLSI implementation. It is shown how the time multiplexed approach can be extended to multiplexing complete filter stages within the tree structure