A DSP-based turbo codec for 3G communication systems

In this paper, we present a high performance Turbo CODEC implemented using digital signal processor for wireless systems following recommended CDMA2000 standard. At the transmitter side, the Turbo encoder is implemented with a modified 15×13 odd-even interleaver. As modern DSP chips, like TI C64x, are designed with multiple functional units, it is important to fully explore the machine-level parallelism to maximize the usage of available computation sources. To this end, at the receiver side, compared to the algorithm used in TI [7], we have redesigned the decoding algorithms with reduced instruction count by 20%. Furthermore, by transforming a number of add/subtract operations to multiplication operations, our decoder can recycle a few functional units previously unused in TI [7]. This Turbo Codec is capable of encoding one frame in 3.1 microseconds and finishing one decoding stage in 18.1 microseconds on a C64x DSP operating at 400 Mhz.