• DocumentCode
    2875031
  • Title

    A storage-node-boosted RAM with word line delay compensation

  • Author

    Fujishima, Kenzaburo ; Shimotori, K. ; Ozaki, Hiroaki ; Nakano, T.

  • Author_Institution
    Mitsubishi Electronic Corp., Itami-shi, Japan
  • Volume
    XXV
  • fYear
    1982
  • fDate
    10-12 Feb. 1982
  • Firstpage
    66
  • Lastpage
    67
  • Abstract
    A dynamic RAM architecture, storing 1.7VDDfor ´1´ level in the cell without any boosted clocks and eliminating the word line delay by means of a pulsed cell plate, will be described.
  • Keywords
    Capacitance; Clocks; DRAM chips; Delay lines; Equivalent circuits; Propagation delay; Read-write memory; Signal detection; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1982.1156385
  • Filename
    1156385
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2875031