Title :
An NMOS DRAM controller
Author :
Bazes, M. ; Nadir, J. ; Perlmutter, D. ; Mantel, B. ; Zak, O.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.
Keywords :
Circuits; Clocks; DRAM chips; Delay; Logic design; MOS devices; Microprocessors; Random access memory; Read-write memory; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156398
