Title :
Analysis of Soft Failures in Low-Resistance Interconnect Vias Using Doubly Nesting Arrays
Author :
Shinkawata, Hiroki ; Sato, Shingo ; Tsuda, Atsushi ; Yoshizawa, Tomoaki ; Ohno, Takio
Author_Institution :
Renesas Electron. Corp., Itami, Japan
Abstract :
An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting array structure. Applying this technique to the development of a 40-nm CMOS technology, a soft failure with about ten times larger than normal via resistance could be efficiently detected and located.
Keywords :
CMOS integrated circuits; failure analysis; integrated circuit interconnections; integrated circuit testing; radiation hardening (electronics); vias; CMOS technology; addressable test structure array; doubly nesting array structure; low-resistance interconnect vias; measurement time; normal via resistance; resistive elements; size 40 nm; soft failures; Computer architecture; Electrical resistance measurement; Kelvin; Resistance; Resistors; Semiconductor device measurement; Time measurement; Array structure; back end of line; interconnect via; soft failure; variation; yield;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2014.2310239
